FRAM Memory Test Software
Memory chips such as Ferroelectric Non Volatile Memory (FRAM) need to be exercised under different operating frequencies, memory read-write cycles, payload, supply voltages, temperature etc for soft error rate tests across their memory range. While the objective is to ascertain zero failures in reading back what the tester wrote, it is also helpful to ascertain when a failure does occur, whether that failure is transient or persistent and whether it is persistent across power cycles too. Additionally, it is desirable to perform this testing across multiple chips in parallel and to manage the entire testing process including the capability for conditional retries in a hardware optimized fashion that is timed as much as possible, in the hardware itself.
​
I2Seebots provides a compact, PXI-based Post Silicon Validation solution that has following features geared towards quick characterization of your FRAM ICs:
​
-
It allows use of either popular protocols such as SPI or specialized custom-built ones supported by a vector definition facility. It tests for memory read/write cycle.
-
It allows one to perform hardware optimized write, read-back and on-the-fly comparisons in a variety of modes; corresponding to different payloads such as checkerboard or inverse checkerboard, user-defined sequence or similar
-
It allow selection of digitized IO levels from a predetermined list or from an externally sourced power/voltage supply
-
It determines reliability of a batch of DUT by testing on representative sample by subjecting it to analog stimulus as required
-
It allows for progressive ramp up or ramp down data rate as per desired user configuration
And particularly for mixed signal chips that also have inbuilt memory, the software has following capabilities:
-
Set up configurable list of power supply devices to be powered as per different user-defined recipes
-
Evaluate any number of DUT pins on-the-fly by using High resolution oscilloscope logs caused by failure condition. These can be flexible and context based and completely configured for pre and post-trigger analog samples as per user requirements
Logging Capability:
​
-
Error locations, timestamps and tagged conditions such as supply voltage, operating frequency etc.
-
Connectivity to SQL databases, customization for internal data repoositories or cloud if desired
Frequently Asked Questions:​
​
1) How many chips can be tested multisite?
A: Only limited by the number of digital and analog channels on the PXI rack. Software can be configured for any number of sites
​
2) What happens to the other DUTs when one of the DUT alone experiences a single event effect?
A: The other DUTs stay idle while retries or power cycles are attempted on the erratic DUT. After the specified number of retries on current memory location, the testing resumes on all DUTs in parallel.
​
3) What is the speed of memory that can be tested?
A. This depends on several factors such as whether retries are needed, the extent of serialization in the memory protocol etc. IN general, the speed can be anything up to 200 Msamples/second of data write/read