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JESD89 Memory Tester for Single Event Effects on Soft Error Rate

The JESD-89 standard lays down a mechanism to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops). The error rate is measured while the device is irradiated in a neutron or proton beam of configurable flux. In the USA, the irradiated testing is often performed in a national or research lab where beam time is quite expensive and therefore careful preparation and lead time is necessary in order to achieve the maximum test outcome from such a visit. Some possible venues for conducting Single Event Effect (SEE) testing in North America are listed here and there are similar venues in other geographies.

 

I2Seebots provides a standardized software solution that has been designed to quickly configure a test setup for SEE testing of a variety of devices such as memories, digital logic devices, power management ICs such as PMICs (See our Single Event Effect Test software for PMICs) etc. Given the cost, preparation and effort of traveling to a radiation test lab, it is useful to test multiple devices in a single visit and then the reconfiguration of the system for those multiple devices must be seamless and rapid. Moreover, hardware and software that is modular and inherently multi-site offers an invaluable advantage for the comprehensiveness of testing and confidence in test results. Importantly, getting more (part numbers, sites) out of one visit has major impact for annualized expenditure on SEE Testing.

 

Features of Software for Multisite, Modular SRAM, DRAM, FRAM Single Event Effect Testing and Single Event Latchup Testing:

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1. Allow setting up a configurable list of power supplies for powering on and off the devices under test. The configured power cycle sequence is applied every time the computer has to determine if a certain Single Event effect is a SEU or a SEL.

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2. Protocol Definition for the memory read/write cycle. Popular protocols such as SPI can be supported off the shelf but custom protocols can also be supported using a simple protocol vector definition facility. I2SeeBots can also provide converters from popular digital vector formats.

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3. Perform hardware optimized Write, Read-back and on-the-fly comparisons in a variety of different modes with a variety of payloads such as Checkerboard, Inverse Checkerboard, User-defined Sequence etc per JESD-89 specified approaches for retries.

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4. Allow selection of digital IO levels from a pre-determined list and also from an external continuous valued IO voltage from a power supply if desired.

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5. Allow set up of analog stimulus as needed to ensure stable operation of the device. This allows the rest of the digital testing to be representative of the real reliability of the DUT when subjected to SEE and SEU stresses.

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6) Control the data rate of the test per desired user configuration. For instance, there are modes to progressively ramp up or down data rate if desired.

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7) Receive fluence and LET data from external programs using the I2Seebot SEE API (either through file mode or image OCR analysis of any external application) or from user as the case may be. Also, log timestamps of the significant digital events so as to correlate with any external records of fluence and LET whose format may vary from one test facility to another. Our OCR capability on the Beam Control Application Image is novel and allows the software to seamlessly interact with beam control programs in different national and research labs with minimal configuration.

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In the case of memories and digital devices, the software has been designed with the necessary flexibility, ease of use and run-time performance to facilitate JESD-89 compliance studies and capture the most meaningful data in the least possible beam time scheduled at National/Research Labs. 

 

In the case of power management ICs, the software has the following features:

 

1. Allow setting up a configurable list of power supplies for powering on and off the devices under test. The configured power cycle sequence is applied every time the computer has to determine if a certain Single Event effect is a SEU or a SEL.

 

2. Allow flexible context-based logging of SEE events with on-the-fly evaluation of  a set of configurable 'failure conditions' that trigger high resolution oscilloscope logs of pre and post trigger analog samples on any number of DUT pins.

 

3. The software can accept details of the fluence, LeT and beam characteristics either from the user or using our API so that the data is tagged for those beam characteristics. Alternatively, I2see bots can also provide custom plugins that will read typical beam characteristic readouts or counters from the specific laboratories and use that information to tag the captured data online or offline for easier data analysis.

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Reporting and logging:

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-Log all errors timestamped with beam conditions and also by temperature if using a temperature controller. The API allows one to add tag information  to accompany the digital test data based on the state of external variables.

-Low timing resolution current/voltage logs (always-on)

-Fine timing resolution current/voltage logs (based on a set of configurable triggers) for chosen number of channels

-Fashion output triggers if necessary for debugging purposes upon any error. Can be used to trigger external capture devices like scopes.

-Issue reproduction facility to I2SeeBots for maintenance or troubleshoot

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Support:   

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I2SeeBots can support customers remotely on hourly or monthly basis.

 

User related :          

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* Authentication feature for different levels of users

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Specifications:

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Commonly Asked Questions:
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1) How many of the same kind of chip can be tested at one time?

A: This is only limited by the number of digital and analog channels on the PXI rack. Software can be configured for any number of sites

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2) What happens to the other DUTs when one of the DUT alone experiences a single event effect?

A: The other DUTs idle while retries or power cycles are attempted on the erratic DUT. After the specified number of retries on current memory location, the testing resumes on all DUTs in parallel.

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3) Who is responsible for load board, PXI and other instrumentation?

A: Customer is ordinarily responsible based on I2SeeBots design recommendations for compatibility with the program. However, other modes are possible- feel free to reach out if you would like to outsource hardware and load boards also.

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4) Will I be able to retain design and source code files for the solution?

A: I2SeeBots provides a license for the software application as well as customization services. Should you request a feature that we cannot add per your budget or timeline expectation, we will also offer source code in our contract so you are always able to extend the program per your specification. Or you can buy the source code outright.

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5) How soon before a facility visit can I start engaging with I2SeeBots and still be sufficiently prepared using I2SeeBots infrastructure.

A: The critical aspect is usually the load board design so it is important to design the right interfaces to the PXI equipment to get maximum leverage from the performance of the system. So 3 months is a good minimum timeframe unless the load board already brings out the right PXI resources in which case even 1 month lead time may be sufficient for a meaningful visit.

Submit form to get immediate budgetary pricing and possible part list for PXI instrumentation (link appears below). We will also respond within a business day to your request wherein you can ask more detailed questions.
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Budgetary Quote for JESD-89 SEE Test Software

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